Clock integrated circuit

ABSTRACT

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

RELATED APPLICATIONS

This application is a continuation of co-pending U.S. application Ser. No. 14/467,419, filed 25 Aug. 2014, which application is a divisional of U.S. application Ser. No. 14/070,303, filed 1 Nov. 2013 (now U.S. Pat. No. 8,819,473), which is a divisional of U.S. application Ser. No. 13/596,953, filed 28 Aug. 2012 (now U.S. Pat. No. 8,589,716), which is a continuation of U.S. application Ser. No. 12/631,705, filed 4 Dec. 2009 (now U.S. Pat. No. 8,261,120). These applications are incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present technology relates to an integrated circuit with a clock circuit, tolerant to variations such as temperature, ground noise, and power noise.

2. Description of Related Art

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Because these variations affect the final timing of the output clock signal, various approaches address the variations in order to generate a uniform output clock signal despite the variations.

For example, U.S. Pat. No. 7,142,005 by Gaboury seeks to decouple power fluctuations from the clock signal, by adding buffer circuits with active loads, independent bias circuitry, and bias circuitry. These relatively complicated buffer circuits devote significantly more die area, and cost, to isolating such power fluctuations from the clock circuit.

What is needed is an approach to address such variations with reduced complexity and cost.

SUMMARY

One aspect of the technology is an apparatus with a clock integrated circuit.

The clock integrated circuit has a timing circuit with an output alternating between a first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit. The second reference signal includes a varying noise signal, such as varying power noise.

The clock integrated circuit also has clock power and reference circuitry, which has the varying noise signal. The clock power and reference circuitry generates the second reference signal with a first version of the varying noise signal. The clock power and reference circuitry also generates a level switching reference signal with a second version of the varying noise signal. The first version of the varying noise signal is synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal.

The clock integrated circuit also has a level switching circuit comparing an output of the timing circuit with the level switching circuit reference signal. An output of the level switching circuit determines the clock signal output of the clock integrated circuit.

In one embodiment, the variations in the first version of the varying noise signal have different magnitudes from the variations in the second version of the varying noise signal.

In one embodiment, the clock power and reference circuitry has a first output for the second reference signal, and a second output for the level switching reference signal, and the varying noise signal is synchronized across the first output and the second output via a resistance coupled between the first output and the second output. In one embodiment, the varying noise signal is synchronized across the first output and the second output via a capacitance coupled between the first output and the second output. In one embodiment, one of the first output and the second output is floating for this capacitive coupling.

One embodiment further includes switches decoupling the level switching circuit during power on.

In one embodiment, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit alternates between charging from the first reference voltage to the second reference voltage and discharging from the second reference voltage to the first reference voltage.

In one embodiment, the time constant characterizes an exponential signal.

In one embodiment, the clock integrated circuit further includes a latch circuit generating the clock signal output of the clock integrated circuit, responsive to the output of the level switching circuit.

Some embodiments include a level switching reference circuit generating the level switching reference signal. The level switching reference circuit includes an output generating the level switching reference signal. In various embodiments the level switching reference circuit includes a PTAT current generator or CTAT current generator, that generates current flowing by the output. In various embodiments the level switching reference circuit includes a resistance adjacent to the output or a parallel resistance and capacitance adjacent to the output.

One aspect of the technology is a clocking method. Some embodiments include the steps of:

determining timing of a clock integrated circuit by alternating a timing circuit output between a first reference signal and a second reference signal at a rate determined by a time constant determining the timing of the clock integrated circuit;

generating the second reference signal with a first version of a varying noise signal and a level switching reference signal with a second version of the varying noise signal, the first version of the varying noise signal synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal; and

comparing the timing circuit output with the level switching reference signal, to determine a clock signal output of the clock integrated circuit.

In some embodiments, the varying noise signal is a varying power noise.

In some embodiments, the variations in the first version of the varying noise signal have different magnitudes from the variations in the second version of the varying noise signal.

In some embodiments, said generating includes:

synchronizing the first version and the second version of the varying noise signal by coupling the second reference signal and the level switching reference signal with a resistance.

In some embodiments, said generating includes:

synchronizing the first version and the second version of the varying noise signal by coupling the second reference signal and the level switching reference signal with a capacitance.

In some embodiments, said generating includes:

synchronizing the first version and the second version of the varying noise signal by floating one of the second reference signal and the level switching reference signal, and coupling the second reference signal and the level switching reference signal with a capacitance.

Some embodiments further include:

decoupling the synchronized versions of the varying noise signal during power on, such that said determining and said comparing do not rely on the synchronized versions of the varying noise signal during power on.

In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit alternates between charging from the first reference voltage to the second reference voltage and discharging from the second reference voltage to the first reference voltage.

In some embodiments, the time constant characterizes an exponential signal.

Some embodiments further include:

after said comparing, generating the clock signal output of the clock integrated circuit with a latch circuit.

One aspect of the technology is a method of manufacturing an apparatus, comprising:

providing a clock integrated circuit, comprising:

providing a timing circuit having an output alternating between a first reference signal and a second reference signal at a rate determined by a time constant determining timing of a clock signal output of the clock integrated circuit, the second reference signal including a varying noise signal;

providing clock power and reference circuitry having the varying noise signal, the clock power and reference circuitry generating the second reference signal with a first version of the varying noise signal, the clock power and reference circuitry generating a level switching reference signal with a second version of the varying noise signal, the first version of the varying noise signal synchronized with the second version of the varying noise signal, such that variations in the first version of the varying noise signal are synchronized with variations in the second version of the varying noise signal; and

providing a level switching circuit comparing an output of the timing circuit with the level switching circuit reference signal, an output of the level switching circuit determining the clock signal output of the clock integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an integrated clock circuit with tolerance to variations such as temperature, ground voltage, and power voltage.

FIGS. 2A and 2B are circuit diagrams of an integrated clock circuit with tolerance to temperature variations, including inverter circuitry to evaluate the timing circuitry output, where FIG. 2A has capacitive timing circuitry coupled towards the ground, and FIG. 2B has capacitive timing circuitry coupled towards power.

FIG. 2C is a circuit diagram of an integrated clock circuit with tolerance to temperature variations, similar to FIG. 2A, but receiving power from PTAT_power sources rather than CTAT_power sources.

FIG. 2D is a circuit diagram of an integrated clock circuit with tolerance to temperature variations, including Schmitt trigger circuitry to perform level detection of the timing circuitry output.

FIG. 2E is a circuit diagram of a Schmitt trigger, such as in FIG. 2D.

FIGS. 3A and 3B are circuit diagrams of an integrated clock circuit with tolerance to temperature variations, including op amp circuitry to perform level detection of the timing circuitry output, where FIG. 3A has capacitive timing circuitry coupled towards the ground, and FIG. 3B has capacitive timing circuitry coupled towards power.

FIG. 4A is a circuit diagram of the circuit for the reference signal for the level detection circuitry including a PTAT current source, with output that decreases with increasing temperature

FIG. 4B is a circuit diagram of the circuit for the reference signal for the level detection circuitry including a CTAT current source, with output that increases with increasing temperature.

FIG. 4C is a circuit diagram of the circuit for the reference signal for the level detection circuitry including a current source, with output that increases with increasing temperature, and further including a capacitor in parallel with a load resistor of a current mirror.

FIG. 4D is a current generator based reference circuit providing PTAT current from PMOS devices.

FIG. 4E is a current generator based reference circuit providing PTAT current from NMOS devices.

FIG. 4F is a current generator based reference circuit providing CTAT current from PMOS devices.

FIG. 4G is a current generator based reference circuit providing CTAT current from NMOS devices.

FIG. 5A is circuit diagram of the circuit for the reference signal for the level detection circuitry including a current source with current output that decreases with increasing temperature, and an output that decreases with increasing temperature.

FIG. 5B is a circuit diagram of the circuit for the reference signal for the level detection circuitry including a current source with current output that increases with increasing temperature, with output that increases with increasing temperature.

FIG. 5C is a circuit diagram of the circuit for the reference signal for the level detection circuitry including a current source with current output that decreases with increasing temperature, with output that increases with increasing temperature.

FIG. 5D is a circuit diagram of the reference signal for the level detection circuitry as in FIG. 5C, but including a current source with current output that increases with increasing temperature.

FIG. 5E is a variation of the circuit of FIG. 5C, where the constant current source replaced with the resistor.

FIG. 6A is a set of graphs of time versus rising magnitude traces showing how clock circuitry that is intolerant of temperature variation generates clock timing that varies widely with varying temperature.

FIG. 6B is a set of graphs of time versus rising magnitude traces showing how clock circuitry that is tolerant of temperature variation generates clock timing is fairly constant with varying temperature, due to circuitry such as that in FIGS. 2-5.

FIG. 7A is a set of graphs of time versus falling magnitude traces showing how clock circuitry that is intolerant of temperature variation generates clock timing that varies widely with varying temperature.

FIG. 7B is a set of graphs of time versus falling magnitude traces showing how clock circuitry that is tolerant of temperature variation generates clock timing is fairly constant with varying temperature, due to circuitry such as that in FIGS. 2-5.

FIGS. 8A and 8B are circuit diagrams of an integrated clock circuit with tolerance to ground noise, including transistors that selectively couple the ground noise as part of the reference signal used in level detection of the timing circuitry output, where in

FIG. 8A the switching reference circuitry include capacitance circuitry coupled towards ground, and in FIG. 8B the switching reference circuitry includes capacitance circuitry coupled towards power.

FIG. 9 is a set of graphs of voltage versus time, showing how clock circuitry that is intolerant of ground noise, will generate clock timing that varies widely with time-varying ground noise.

FIG. 10 is a set of graphs of voltage versus time, showing how clock circuitry that is tolerant of ground noise, will generate clock timing that is fairly constant with time-varying ground noise, due to circuitry such as that in FIG. 8.

FIGS. 11A and 11B are circuit diagrams of an integrated clock circuit with tolerance to power noise, including transistors that share a common noise phase of power noise in the timing circuitry power, and power noise in the reference signal used in level detection of the timing circuitry output, where in FIG. 11A the capacitance circuitry is coupled towards ground, and in FIG. 11B the capacitance circuitry is coupled towards power.

FIG. 12 is a circuit diagram of the power circuitry that shares the common noise phase of power noise to in the timing circuitry power, and power noise to in the reference signal used in level detection of the timing circuitry output.

FIG. 13 is a set of graphs of voltage versus time, showing how power noise has the same phase in both the timing circuitry power, and the reference signal used in level detection of the timing circuitry output, due to circuitry such as in FIGS. 11 and 12.

FIG. 14 is a set of graphs of voltage versus time, showing how clock circuitry that is intolerant of power noise, will generate clock timing that varies widely with time-varying power noise.

FIG. 15 is a set of graphs of voltage versus time, showing how clock circuitry that is tolerant of power noise, will generate clock timing that is fairly constant with time-varying power noise, due to circuitry such as that in FIGS. 11 and 12.

FIGS. 16A and 16B are circuit diagrams of an integrated clock circuit with tolerance to power noise, including transistors that share a common noise phase of power noise in the timing circuitry power, and power noise in the reference signal used in level detection of the timing circuitry output, similar to FIG. 11, and adding switch circuitry to selectively bypass the noise tolerant circuitry, such as during power on.

FIG. 17 is block diagram of a memory circuit with an improved integrated clock circuit as discussed herein.

FIG. 18 is a circuit diagram, similar to FIG. 16, of an integrated clock circuit with tolerance to power noise, and further including switching circuitry between the reference generator and the op amp.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of an integrated clock circuit with tolerance to variations such as temperature, ground voltage, and power voltage.

The clock integrated circuit generally has a loop structure, with timing circuitry 102, level switching circuitry 104, and latch circuitry 106. The latch circuitry 106 generates a feedback signal from latch circuitry 106 back to timing circuitry 102, and the clock signal output 110. The timing circuitry 102 alternates between two reference signals according to a time constant. The time constant accordingly determines the timing of the clock integrated circuit. A typical example of the time constant is an exponential time constant that characterizes the rise and fall of an RC circuit or an RL circuit. The level switching circuitry monitors the output of the timing circuitry 102, and changes the output depending on whether the timing circuitry 102 is sufficiently high, or low. Examples of latch circuitry 106 are an SR latch, SR NAND latch, JK latch, gated SR latch, gated D latch, gated toggle latch. The latch circuitry 106 has two stable states and alternates between the two stable states to generate the clock signal output 110.

The two reference signals relied on by the timing circuitry 102 are generated by circuitry 116, which also generates the level switching reference relied on by the level switching circuitry 104. By commonly generating both the reference signals relied on by the timing circuitry 102, and the level switching reference relied on by the level switching circuitry 104, circuitry 116 minimizes the noise phase of a noise signal shared by the reference signals relied on by the timing circuitry 102, and the level switching reference relied on by the level switching circuitry 104. Because any noise phase is minimal, peaks and valleys in the noise signal that occur in the reference signals relied on by the timing circuitry 102, are synchronous with peaks and valleys in the noise signal that occur in the level switching reference relied on by the level switching circuitry 104.

The level switching reference 112 relied on by the level switching circuitry 104, is selectively coupled to the level switching circuitry 104 by circuitry 118. In some embodiments, this acts as a sample and hold of ground noise, so that the same ground noise is held by the timing circuitry 102, and by the level switching reference circuitry relied on by the level switching circuitry 104.

Although the shown block diagram addresses the variations in temperature, ground noise, and power noise, various embodiments of an improved clock integrated circuit address just one of these variations (e.g., just temperature, just power noise, or just ground noise), or just two of these variations (e.g., just temperature and power noise, just temperature and ground noise, or just power noise and ground noise).

FIGS. 2A and 2B are circuit diagrams of an integrated clock circuit with tolerance to temperature variations, including inverter circuitry to evaluate the timing circuitry output.

Shown are parallel instances of timing circuitry 202A and 202B, parallel instances of inverter circuitry 204A and 204B, and the latch circuitry 206. The timing circuitry 202A and 202B is generally an inverter with resistance RX or RY, charging to or discharging from capacitance CX or CY, to change the output voltage at OX or OY.

FIG. 2A shows an embodiment where the capacitance CX or CY is coupled to a common ground. Although all possible variations are not explicitly shown in the Figures, the present technology covers all disclosed instances of the clock circuit showing the capacitance CX or CY, where the clock circuit is modified to couple the capacitance CX or CY to ground.

In one embodiment, the capacitance CX or CY is actually a PMOS transistor with the opposite terminal decoupled from a common ground with the inverters.

FIG. 2B shows an embodiment where the capacitance CX or CY is coupled to a common power. Although all possible variations are not explicitly shown in the Figures, the present technology covers all disclosed instances of the clock circuit showing the capacitance CX or CY, where the clock circuit is modified to couple the capacitance CX or CY to a common power.

In one embodiment, the capacitance CX or CY is actually a PMOS transistor with the opposite terminal decoupled from a common power with the inverters.

The inverter circuitry 204A and 204B is driven by a source of CTAT_power, or power that is conversely proportional to temperature, to decrease with increasing temperature.

The inverters are very different from the op amp version. In the op amp version, a Vref is compared against the timing circuit output (e.g., RC circuit rise/fall). But in the inverter version, the power of the inverter is controlled, to change the trip point of the inverter and thereby detect the timing circuit output (e.g., RC circuit rise/fall). In the inverter version, an additional temperature relationship between the power and the trip point of the inverter is of concern.

The inverters are advantageous over the op amp version, for one or more of the following reasons: (1) lower working VDD; (2) smaller circuit size (inverter has only 2 MOSFETs, but the op amp has 5 or more MOSFETs). (3) simpler design; (4) lower active current (inverter has one current path, but the op amp has 2 or 3 current paths and includes an extra current mirror); and (5) higher speed (inverter has one stage delay, the op amp has 2 or 3 stages of delay).

The latch circuitry 206 is cross-coupled, such that the output of one gate is coupled to the inputs of the other gate. One input of a gate is directly coupled to the output of another gate. Another input of a gate is directly coupled to the output of another gate through the timing circuitry and the level detection circuitry.

FIG. 2C shows another embodiment of a clock circuit. Although otherwise similar to FIG. 2A, in FIG. 2C the parallel instances of inverter circuitry 204A and 204B are driven by sources of PTAT_power, or power that is proportional to temperature, to increase with increasing temperature. Although all possible variations are not explicitly shown in the Figures, the present paper covers instances of the clock circuit showing a source of CTAT_power, where the source of CTAT_power is replaced with a source of PTAT_power.

Similarly, although all possible variations are not explicitly shown in the Figures, the present paper covers all disclosed instances of the clock circuit showing a source of PTAT_power, where the source of PTAT_power is replaced with a source of CTAT_power.

FIG. 2D is a diagram of an integrated clock circuit with tolerance to temperature variations, including Schmitt trigger circuitry to evaluate the timing circuitry output.

Although similar to FIG. 2B, in FIG. 2D the level switching circuitry 210A and 210B are instances of a Schmitt trigger driven by a source of CTAT_power, and include op amps with closed loop positive feedback through resistance.

FIG. 2E is a diagram of a Schmitt trigger circuit.

FIG. 3 is a circuit diagram of an integrated clock circuit with tolerance to temperature variations, including OP amp circuitry to perform level detection of the timing circuitry output by comparison with a reference.

Shown are parallel instances of timing circuitry 302A and 302B, parallel instances of level switching circuitry 304A and 304B, and the latch circuitry 306. The level switching circuitry 304A and 304B are OP amp comparator with a reference voltage CTAT_REF. Otherwise, the clock circuit is generally similar to FIG. 2A.

FIG. 4A is circuit diagram of the reference signal for the level detection circuitry, including a current source with current output that increases with increasing temperature.

FIG. 4A shows how the CTAT_power signal relied on by the level detection circuitry is generated, shown here as CTAT_REF 428. A constant current source PTAT_I 426, draws current that is proportional to temperature, to increase with increasing temperature, from regulated power 422 through resistor RES 424. The regulated power 422 supplies a constant voltage independent of varying temperature. The regulated power supplies a constant power and does not change with the VDD and temperature. An example is the output of a regulator with a bandgap reference. The resulting output is conversely proportional to temperature, due to the increasing voltage drop across the resistor with increasing temperature and the placement of the output terminal on the lower side of this voltage drop. An example of the current source is shown in FIG. 4E.

FIG. 4B is a variation of the circuit of FIG. 4A, where the constant current source PTAT_I 426 is replaced with the constant current source CTAT_I 430, and the CTAT_power signal CTAT_REF 428 relied on by the level detection circuitry is replaced with PTAT_power signal PTAT_REF 432 relied on by the level detection circuitry. An example of: the current source is shown in FIG. 4G.

FIG. 4C is a variation of the circuit of FIG. 4A, with a bypass capacitor 434 in parallel with resistor RES 424, which decreases the noise. Also, the current source includes a current mirror. An example of the current source circuit is shown in FIG. 4D.

FIG. 4D is a current generator based reference circuit providing PTAT current from PMOS devices.

FIG. 4E is a current generator based reference circuit providing PTAT current from NMOS devices.

In FIGS. 4D and 4E, the circuit uses the delta_Vgs between two MOS transistors having the same current, proportional to temperature. So delta_Vgs/resistance=PTAT_I. In FIGS. 4D and 4E, these two transistors are identified with circles.

FIG. 4F is a current generator based reference circuit providing CTAT current from PMOS devices.

FIG. 4G is a current generator based reference circuit providing CTAT current from NMOS devices.

A current generator based reference circuit as described herein is advantageous, because in several embodiments, a single kind of temperature dependent parameter is controlled, instead of two kinds of temperature dependent parameters associated with different materials having different temperature dependence.

FIG. 5A is circuit diagram of the reference signal for the level detection circuitry, including a current source with current output that decreases with increasing temperature.

FIG. 5A shows how the CTAT_power signal relied on by the level detection circuitry is generated, shown here as CTAT_REF 528. A constant current source CTAT_I 526, draws current that is conversely proportional to temperature, to decrease with increasing temperature, from regulated power 522 through resistor RES 524. The resulting output is conversely proportional to temperature, due to the decreasing voltage drop across the resistor with increasing temperature and the placement of the output terminal on the upper side of this voltage drop.

An example of the shown current sources is a cascade current source.

FIGS. 5B, 5C, 5D, and 5E are other examples to generate the reference voltage signal.

FIG. 5B is a variation of the circuit of FIG. 5A, where the constant current source CTAT_I 526 is replaced with the constant current source PTAT_I 530, and the CTAT_power signal CTAT_REF 528 relied on by the level detection circuitry is replaced with PTAT_power signal PTAT_REF 532 relied on by the level detection circuitry.

FIG. 5C is a variation of the circuit of FIG. 5A, where the resistor RES 524 is replaced with the diode DI0 530. An example of the current source is shown in FIG. 4F.

FIG. 5D is a variation of the circuit of FIG. 5C, where the constant current source CTAT_I 526 is replaced with the constant current source PTAT_I 530, and the placement of the output terminal is moved from the upper side of the voltage drop across the constant current source, to the lower side of the voltage drop across the constant current source.

FIG. 5E is a variation of the circuit of FIG. 5C, where the constant current source CTAT_I 526 is replaced with the resistor RES 524.

FIG. 6A is a set of graphs of time versus magnitude traces showing how clock circuitry that is intolerant of temperature variation generates clock timing that varies widely with varying temperature.

FIG. 6A shows a range of traces at high temperature, low temperature, and intermediate temperature. The lower the temperature, the faster the timing circuitry becomes, and the higher the temperature, the slower the timing circuitry becomes. Due to the common timing circuitry reference, the timing circuitry reaches the reference more quickly at low temperature than at high temperature. Consequently, the timing of the clock circuitry is faster at low temperature than at high temperature.

FIG. 6B is a set of graphs of time versus magnitude traces showing how clock circuitry that is tolerant of temperature variation generates clock timing is fairly constant with varying temperature, due to circuitry such as that in FIGS. 2-5.

FIG. 6B shows a range of traces at high temperature, low temperature, and intermediate temperature. As in FIG. 6A, the lower the temperature, the faster the timing circuitry becomes, and the higher the temperature, the slower the timing circuitry becomes. However, different timing circuitry references are used in FIG. 6B, in contrast with the common timing circuitry reference used in FIG. 6A. Although the timing circuitry reaches the reference more quickly at low temperature than at high temperature, the timing circuitry reference is also correspondingly higher. Consequently, the timing of the clock circuitry shows little variation despite the temperature variation and resulting speed variation in the timing circuitry.

FIGS. 7A and 7B are other embodiments, which show falling signals rather the rising signals of FIGS. 6A and 6B, but still show the same time constants.

Whether a clock signal relies on rising signals such as FIGS. 6A and 6B, or falling signals such as FIGS. 7A and 7B, depends on whether the capacitance CX and CY is coupled towards ground as in FIG. 2A or towards power as in FIG. 2B.

FIGS. 8A and 8B are circuit diagrams of an integrated clock circuit with tolerance to ground noise, including transistors that selectively couple the ground noise as part of the reference signal used in level detection of the timing circuitry output.

Shown are parallel instances of timing circuitry 802A and 802B, parallel instances of level switching circuitry 804A and 804B, and the latch circuitry 806. The level switching circuitry 804A and 804B selectively couples the ground noise coming from the level switching reference circuitry 816A or 816B, and is stored in the capacitive node REF X or REFY, respectively subject to the switching action of the switching transistor 818A turned on by signal ENX and the switching transistor 818B turned on by signal ENY. This acts as a sample and hold of ground noise, so that the same ground noise is held by the timing circuitry 802A or 802B, and by the level switching reference circuitry reference nodes REFX or REFY, relied on by the level switching circuitry 104.

In one embodiment, the capacitance CX or CY is actually a PMOS transistor with the opposite terminal decoupled from a common power with the PMOS which connects to the RX or RY

OX is kept at ground when ENX is high. Then ENX goes low and turns off the NMOS; at this moment the ground noise is held in the OX. If the noise is high then the pre-charge speed is fast; if the noise is low then the pre-charge speed is slow. This circuit lets the REFX or REFY hold the same ground noise at the same time.

In FIG. 8A the switching reference circuitry reference nodes REFX or REFY, includes capacitance circuitry coupled towards ground. In FIG. 8B the switching reference circuitry reference nodes REFX or REFY, includes capacitance circuitry coupled towards power.

In various embodiments, the level switching reference circuitry 816A or 816B are two sets of circuitry, or the same set of circuitry shared by the multiple parallel instances of timing circuitry and the multiple level switching circuitry 804A and 804B.

FIG. 9 is a set of graphs of voltage versus time, showing how clock circuitry that is intolerant of ground noise, will generate clock timing that varies widely with time-varying ground noise.

FIG. 9 shows how traces OX and OY are affected by ground noise, in this case the REF_LO signal. When there is a peak in ground noise, then the process of the timing circuit charging from REF_LO to REF_HI gets a head start, resulting in less time being required for the timing circuit to charge from REF_LO to REF_HI. Accordingly, the resulting clock signal output 910 has a wide variation in clock period.

When ENX goes high, the OX is kept at ground and the voltage varies with the ground noise. When ENX goes low, and turns off the NMOS, then the ground noise is kept at the OX. But the reference level still varies with the ground noise without more. The worse case is that OX holds a high ground noise and during the charging period the reference circuit suffer a negative ground level; then the reference is much lower than expected. So a sample and hold like structure keeps the same ground noise in the REFX or REFY.

FIG. 10 is a set of graphs of voltage versus time, showing how clock circuitry that is tolerant of ground noise, will generate clock timing that is fairly constant with time-varying ground noise, due to circuitry such as that in FIG. 8.

FIG. 10 shows how traces OX and OY are affected by ground noise, in this case the REF_LO signal. When there is a peak or other variation in ground noise, this peak or other variation is stored in the respective capacitor for REFX or REFY of FIG. 8. Because ground noise affecting REF_LO is tracked by this sample-and-hold reference circuitry, the level detection circuitry compares the same ground noise from the level detection reference circuitry, and the timing circuitry. After the ground noise is sampled and held in this manner, the ground noise, which continued to change, is decoupled from the sampling circuitry. Accordingly, in the process of the timing circuit charging from REF_LO to REF_HI, there is no “head start”, and the same time is required for the timing circuit to charge from REF_LO to REF_HI, despite the ground noise. Accordingly, the resulting clock signal output 910 has a common clock period during a wide variation in ground noise.

Another embodiment is directed to sampling the ground noise and then decoupling the ground noise from the sampling circuitry during discharging, rather than decoupling the ground noise from the sampling circuitry during charging as in FIGS. 9 and 10. This embodiment carries the additional difficulty of having to address power noise from the noise regulator power.

In another embodiment (like FIG. 2C), the sample and hold circuit will hold the power noise instead of the ground noise.

FIGS. 11A and 11B are circuit diagrams of an integrated clock circuit with tolerance to power noise, including transistors that share a common noise phase of power noise in the timing circuitry power, and power noise in the reference signal used in level detection of the timing circuitry output.

Shown are parallel instances of timing circuitry 1102A and 1102B, parallel instances of level switching circuitry 1104A and 1104B, and the latch circuitry 1106. Also shown are parallel instances of timing power and level switching generator 1116A and 1116B, which generate power noise with the same noise phase in both the power noise in the timing circuitry power, and the power noise in the reference signal used in level detection of the timing circuitry output.

In FIG. 11A the capacitance circuitry CX or CY is coupled towards ground. In FIG. 11B the capacitance circuitry CX or CY is coupled towards power 1116A or 1116B.

FIG. 12 is a circuit diagram of the power circuitry that shares the common noise phase of power noise in the timing circuitry power, and power noise in the reference signal used in level detection of the timing circuitry output.

FIG. 12 shows a power source 1236, driving an op amp 1232. The op amp has a reference signal REF_OP 1234 in the noninverting input. An example of REF_OP 1234 is a bandgap reference circuit at 1.3 V. A MOFET 1238 has a gate coupled to the output of op amp 1232, a drain coupled to the power source 1236, and a source coupled to the timing power output 1246. The timing power output 1246 is separated by resistor R1 1240 from the level switching reference 1248. Resistor R2 1242 separates the level switching reference 1248 from the negative feedback point of the op amp 1232. Finally, resistor R3 couples this feedback point to ground.

Another embodiment employs capacitive coupling with a floating node to maintain the same noise phase between the timing power output 1246 and the level switching reference 1248, where one of the timing power output 1246 and the level switching reference 1248 is floating.

Although the above embodiments are specifically designed to maintain the same noise phase between the timing power output 1246 and the level switching reference 1248, this is not the case in other designs. Such other designs have different noise phase between the timing power output and the level switching reference 1248, for one or more various reasons: (1) the reference circuit is not near the timing circuit due to the chip plan; (2) the reference circuit is a regulator which has better PSRR (power supply rejection ratio) than VDD power; and (3) even with a power regulator for the RC power, a noise phase difference remains, due to the different output loading and transient, and the power regulator having to support larger current and larger output transient.

FIG. 13 is a set of graphs of voltage versus time, showing how power noise has the same phase in both the timing circuitry power, and the reference signal used in level detection of the timing circuitry output, due to circuitry such as in FIGS. 11 and 12.

The same noise phase is shown in both the power noise in the timing circuitry power 1301, and the power noise in the reference signal used in level detection of the timing circuitry output 1302. Trace 1303 overlaying traces 1301 and 1302 show that, although the magnitudes of the power noise vary, the peaks and valleys are synchronous in the power noise between traces 1301 and 1302.

FIG. 14 is a set of graphs of voltage versus time, showing how clock circuitry that is intolerant of power noise, will generate clock timing that varies widely with time-varying power noise.

FIG. 14 shows how traces OX and OY are affected by power noise 1401. When there is a dip in power noise, then the process of the timing circuit charging from REF_LO to REF_HI gets a head start, resulting in less time being required for the timing circuit to charge from REF_LO to REF_HI. Similarly, when there is a peak in power noise, then the process of the timing circuit charging from REF_LO to REF_HI gets slowed, resulting in more time being required for the timing circuit to charge from REF_LO to REF_HI. These variations follow from the constant level switching reference. Accordingly, the resulting clock signal output 1410 has a wide variation in clock period.

FIG. 15 is a set of graphs of voltage versus time, showing how clock circuitry that is tolerant of power noise, will generate clock timing that is fairly constant with time-varying power noise, due to circuitry such as that in FIGS. 11 and 12.

FIG. 15 shows how traces OX and OY are affected by ground noise. Unlike in FIG. 14, when there is a peak or other variation in power noise 1501, there is a a synchronous has peak or other variation in the level switching reference. Although the magnitude of these peaks or other variations are lessened in the level switching reference, as compared to that of the power noise, the synchronous nature of the power noise between the timing circuitry power 1501 and the level switching reference substantially decreases the clock signal variation. Accordingly, the resulting clock signal output 1510 has a common clock period during a wide variation in ground noise.

FIGS. 16A and 16B are circuit diagrams of an integrated clock circuit to switch the power of the clock. During power on, the stable power isn't ready, and needs the VDD power to generate the clock for the logic circuits. Logic circuitry waits for the stable power setup timing. When the stable power is ready, then the clock will switch to a stable clock.

Shown are parallel instances of timing circuitry 1602A and 1602B, parallel instances of level switching circuitry 1604A and 1604B, and the latch circuitry 1606. Also shown are parallel instances of timing power and level switching generator 1616A and 1616B, which generate power noise with the same noise phase in both the power noise in the timing circuitry power, and the power noise in the reference signal used in level detection of the timing circuitry output. Also shown are switches 1620A between the VDD and the timing power and level switching generator 1616A, switches 1620B between the VDD and the timing power and level switching generator 1616B, switches 1620C between different types of level switching circuitry 1604A and the latch 1606, and switches 1620D between different types of level switching circuitry 1604B and the latch 1606.

In FIG. 16A the capacitance circuitry CX or CY is coupled towards ground. In FIG. 16B the capacitance circuitry CX or CY is coupled towards power 1616A or 1616B.

FIG. 17 is block diagram of a memory circuit with an improved integrated clock circuit as discussed herein.

FIG. 17 is a simplified block diagram of an integrated circuit 1700 including a memory array 1712. A word line (or row) and block select decoder 1714 is coupled to, and in electrical communication with, a plurality 1716 of word lines and string select lines, and arranged along rows in the memory array 1712. A bit line (column) decoder and drivers 1718 are coupled to and in electrical communication with a plurality of bit lines 1720 arranged along columns in the memory array 1712 for reading data from, and writing data to, the memory cells in the memory array 1712. Addresses are supplied on bus 1722 to the word line decoder and drivers 1714 and to the bit line decoder 1718. Sense amplifiers and data-in structures in block 1724, including current sources for the read, program and erase modes, are coupled to the bit line decoder 1718 via the bus 1726. Data is supplied via the data-in line 1728 from input/output ports on the integrated circuit 1710, to the data-in structures in block 1724. In the illustrated embodiment, other circuitry 1730 is included on the integrated circuit 1700, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory cell array. Data is supplied via the data-out line 1732 from the sense amplifiers in block 1724 to input/output ports on the integrated circuit 1700, or to other data destinations internal or external to the integrated circuit 1700. State machine and improved clock circuitry (as discussed herein) are in circuitry 1734.

FIG. 18 is a circuit diagram, similar to FIG. 16, of an integrated clock circuit with tolerance to power noise, and further including switching circuitry between the reference generator and the op amp. As in FIG. 8, the switching transistor 818A is turned on by signal ENX and the switching transistor 818B is turned on by signal ENY. Similar to FIG. 8, ground noise coming from the timing power and level switching generator 1616A and 1616B is stored in the capacitive node REF X or REFY.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. 

What is claimed is:
 1. An apparatus, comprising: an integrated circuit with clock power and reference circuitry, including: a first regulating element receiving power and generating regulated power received by a timing circuit, the timing circuit having a first output; and a second regulating element generating a regulated level switching reference signal based upon the regulated power, the regulated level switching reference signal sent to a level switching circuit, the level switching circuit having a second output; and wherein the first output and the second output are different electrical nodes.
 2. The apparatus of claim 1, further comprising: the timing circuit having an output alternating between a first reference signal and the regulated power signal at a rate determined by a time constant determining timing of a clock signal output; and the level switching circuit comparing the regulated level switching reference signal with the output of the timing circuit, such that an output of the level switching circuit determines the clock signal output.
 3. The apparatus of claim 2, wherein the regulated power and the regulated level switching reference signal share a same noise phase of a noise signal in the power received by the first regulating element.
 4. The apparatus of claim 2, wherein the regulated power and the regulated level switching reference signal have different noise magnitudes of a noise signal in the power received by the first regulating element.
 5. The apparatus of claim 1, further comprising: an operation amplifier receiving at a first input a first reference voltage, and receiving at a second input a feedback signal from a circuit loop including the first regulating element and the second regulating element.
 6. An apparatus, comprising: a reference circuit, coupled to a ground, generating a reference signal including a first ground noise signal based on a ground having a ground having a ground noise; a timing circuit generating a timing signal including a second ground noise signal based on said ground noise, and further comprising a first capacitor having a first end coupled to said ground or a power, and a second end coupled to the timing signal; and a comparator receiving at a first input the reference signal, and receiving at a second input the timing signal, and providing an output signal; and wherein the first ground noise signal and in the second ground noise signal are offset to decouple the ground noise from the output signal of the comparator.
 7. The apparatus of claim 6, wherein the reference circuit further comprises: a second capacitor having a first end coupled to said ground or said power and a second end coupled to the first input of the comparator.
 8. The apparatus of claim 7, wherein the reference circuit further comprises: a second capacitor having a first end and a second end, the first end coupled to said power or to said ground; a reference circuit generating a reference voltage at a reference voltage output; and a switch having a first terminal, a second terminal, and a control terminal, the first terminal coupled to the reference voltage output of the reference circuit, the second terminal coupled to second end of the second capacitor, and a control signal coupled to the control terminal.
 9. The apparatus of claim 8, wherein the control signal is synchronized with an input signal of the timing circuit.
 10. The apparatus of claim 6, wherein the timing signal alternates between a first level and a second level at a rate determined by an exponential time constant determining timing of the output signal of the comparator.
 11. The apparatus of claim 9, wherein the control signal controls charging times of the first capacitor, and when the control signal is in one state, the switch switches off to decouple the second capacitor from the reference circuit, while the second capacitor keeps the second ground noise signal.
 12. The apparatus of claim 9, wherein the control signal controls discharging of the first capacitor, and when the control signal is in one state, the switch switches off to decouple the second capacitor from the reference circuit while the second capacitor keeps the second ground noise signal.
 13. The apparatus of claim 6, wherein the comparator comprises an operational amplifier.
 14. A method, comprising: receiving power and ground, the ground including ground noise; generating a level switching reference signal which includes a first ground noise signal based on the ground noise; generating a timing signal which includes a second ground noise signal based on the ground noise; comparing the timing signal to the level switching reference signal to generate an output signal, wherein the first ground noise signal and the second ground noise signal are offset to decouple the output signal from the ground noise.
 15. The method of claim 14, including generating the timing signal using a first capacitor having a first end coupled to said ground or a power, and a second end coupled to the timing signal, the first capacitor capturing noise based on the second ground noise signal.
 16. The method of claim 15, including applying the level switching reference signal to a first end of a second capacitor, the second capacitor having a second end coupled to said ground or said power, the second capacitor capturing noise based on the first ground noise signal.
 17. The method of claim 16, including connecting and disconnecting the level switching reference signal from the first end of the second capacitor using a switch controlled by a control signal.
 18. The method of claim 17, synchronizing the control signal with an input signal used to control the generating of the timing signal.
 19. The method of claim 18, generating the control signal using the output signal.
 20. The method of claim 14, including comparing the timing signal to the level switching reference signal using an operational amplifier. 